1. Field of the Invention
The present invention relates to a memory controller, a memory system and a method of adjusting a time position of a data transfer from a memory controller to a memory circuit.
2. Description of the Related Art
In memory systems data are delivered from a memory controller to a memory circuit. For attaining a high frequency for transmitting data to the memory circuit, it is necessary to align the phase of the transmitted data to an internal receiving clock of the memory circuit precisely. If the internal clock of the memory circuit and the data do not have a certain phase relationship at a sampling point of the memory circuit, an error-free data transfer cannot be guaranteed. Reduced timing budgets to higher data rates make these requirements to the phase alignment even harder.
An automatic adjustment mechanism may reduce in conventional methods the static mismatches between the propagations paths of the internal clock of the memory circuit and each data signal individually. Even voltage and temperature dependent drifts may be compensated to a certain level by continuous or periodic readjustment. For such an automatic mechanism to work, knowledge about the actual phase relationship of the internal clock and the data in the DRAM is needed. Current DRAM standards do not provide any mechanism for returning this information to the memory controller.
Conventional memory controllers solve this issue by making a set of functional tests with respect to the memory circuit. After writing specific data pattern with differently skewed phases into the memory circuit storage array and reading back, the data phase window with error-free transition is identified and an optimum write phase is chosen. For a certain level of drift tracking capability, this phase training must be redone periodically.